AI & Machine Learning, Multimedia Signal Processing, Information, Communication & Coding, Computer Architecture, Software Systems & Networking, Integrated Circuits & Semiconductor Systems
주요 연구
VLSI signal processing, Digital system-on-chip design, Application-specific processor, Algorithm-hardware co-design methodology
“FIGLUT: An energy-efficient accelerator design for FP-INT GEMM using look-up tables,” IEEE International Symposium on High-Performance Computer Architecture (HPCA), Mar. 2025.
“Panacea: Novel DNN accelerator using accuracy-preserving asymmetric quantization and energy-saving bit-slice sparsity,” IEEE International Symposium on High-Performance Computer Architecture (HPCA), Mar. 2025.
“Energy-efficient flexible RNS-CKKS processor for FHE-based privacy-preserving computing,” IEEE Journal of Solid-State Circuits, Jan. 2025.
“A 43.9 μs IRS controller SoC with grid-based phase-shift optimization in 28 nm CMOS technology for next-generation communication,” IEEE Transactions on Circuits and Systems I: Regular Papers, July 2024.
“LUT-GEMM: Quantized matrix multiplication based on LUTs for efficient inference in large-scale generative language models,” International Conference on Learning Representations (ICLR), May 2024.
“A 21.9 ns, 15.7 Gbps/mm^2 (128, 15) BOSS FEC decoder for 5G/6G URLLC applications,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2024.
