{"id":151243,"date":"2023-11-16T10:23:01","date_gmt":"2023-11-16T01:23:01","guid":{"rendered":"http:\/\/ee.presscat.kr\/?post_type=research-achieve&#038;p=151243"},"modified":"2026-04-13T12:58:10","modified_gmt":"2026-04-13T03:58:10","slug":"m-s-course-jiwon-choi-prof-hoi-jun-yoo-won-the-best-design-award-at-2023-ieee-a-sscc","status":"publish","type":"research-achieve","link":"http:\/\/ee.presscat.kr\/en\/research-achieve\/m-s-course-jiwon-choi-prof-hoi-jun-yoo-won-the-best-design-award-at-2023-ieee-a-sscc\/","title":{"rendered":"M.S. Course Jiwon Choi (Prof. Hoi-Jun Yoo), won the Best Design Award at 2023 IEEE A-SSCC"},"content":{"rendered":"<p><span style=\"font-size: 14pt\"><strong><span style=\"font-family: verdana, geneva, sans-serif;color: #000000\">M.S. Course Jiwon Choi (Prof. Hoi-Jun Yoo), won the Best Design Award at 2023 IEEE A-SSCC<\/span><\/strong><\/span><\/p>\n<p>&nbsp;<\/p>\n<p><span style=\"font-family: verdana, geneva, sans-serif;color: #000000\"><img fetchpriority=\"high\" decoding=\"async\" class=\"alignnone size-full wp-image-151244\" src=\"http:\/\/ee.presscat.kr\/wp-content\/uploads\/2023\/11\/Inline-image-2023-11-15-14.17.37.356-1.jpg\" alt=\"\" width=\"867\" height=\"355\" title=\"\"><\/span><\/p>\n<div><span style=\"font-family: verdana, geneva, sans-serif;color: #000000\">&lt;Certificate of Award &amp; Award Ceremony&gt;<\/span><\/div>\n<div>\u00a0<\/div>\n<p><span style=\"font-family: verdana, geneva, sans-serif;color: #000000\">M.S. student Jiwon Choi\u00a0(Advised by Hoi-Jun Yoo) won the Best Design Award at the 2023 IEEE\u00a0Asian Solid-State Circuits Conference (A-SSCC) Student Design Contest. <\/span><\/p>\n<p><span style=\"font-family: verdana, geneva, sans-serif;color: #000000\">The conference was held in Hainan, China from November 5th to 8th. A-SSCC is an international conference held annually by IEEE. M.S. student\u00a0Jiwon Choi\u00a0has published a paper titled\u00a0\u201cA Resource-Efficient Super-Resolution FPGA Processor with Heterogeneous CNN and SNN Core Architecture\u201d.<\/span><\/p>\n<p>&nbsp;<\/p>\n<p><span style=\"font-family: verdana, geneva, sans-serif;color: #000000\">Details are as follows.\u00a0<\/span><\/p>\n<p>&nbsp;<\/p>\n<p><span style=\"font-family: verdana, geneva, sans-serif;color: #000000\">Conference:\u00a02023 IEEE Asian Solid-State Circuits Conference (A-SSCC)<\/span><\/p>\n<p><span style=\"font-family: verdana, geneva, sans-serif;color: #000000\">Date: November 5-8, 2023<\/span><\/p>\n<p><span style=\"font-family: verdana, geneva, sans-serif;color: #000000\">Award:\u00a0Best Design Award<\/span><\/p>\n<p><span style=\"font-family: verdana, geneva, sans-serif;color: #000000\">Authors: Jiwon Choi, Sangyeob Kim, Wonhoon Park, Wooyoung Jo, and Hoi-Jun Yoo (Advisory Professor)<\/span><\/p>\n<p><span style=\"font-family: verdana, geneva, sans-serif;color: #000000\">Paper Title:\u00a0A Resource-Efficient Super-Resolution FPGA Processor with Heterogeneous CNN and SNN Core Architecture<\/span><\/p>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>694<\/p>\n","protected":false},"featured_media":151296,"template":"","research_category":[],"class_list":["post-151243","research-achieve","type-research-achieve","status-publish","has-post-thumbnail","hentry"],"acf":[],"_links":{"self":[{"href":"http:\/\/ee.presscat.kr\/en\/wp-json\/wp\/v2\/research-achieve\/151243","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/ee.presscat.kr\/en\/wp-json\/wp\/v2\/research-achieve"}],"about":[{"href":"http:\/\/ee.presscat.kr\/en\/wp-json\/wp\/v2\/types\/research-achieve"}],"wp:featuredmedia":[{"embeddable":true,"href":"http:\/\/ee.presscat.kr\/en\/wp-json\/wp\/v2\/media\/151296"}],"wp:attachment":[{"href":"http:\/\/ee.presscat.kr\/en\/wp-json\/wp\/v2\/media?parent=151243"}],"wp:term":[{"taxonomy":"research_category","embeddable":true,"href":"http:\/\/ee.presscat.kr\/en\/wp-json\/wp\/v2\/research_category?post=151243"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}