{"id":195820,"date":"2025-06-02T16:34:06","date_gmt":"2025-06-02T07:34:06","guid":{"rendered":"http:\/\/ee.presscat.kr\/?post_type=press-post&p=195820"},"modified":"2026-04-18T00:05:42","modified_gmt":"2026-04-17T15:05:42","slug":"ai-memory-chip-guru-to-unveil-road-map-for-next-generation-hbmskorea-times-25-05-29","status":"publish","type":"press-post","link":"http:\/\/ee.presscat.kr\/en\/presses\/ai-memory-chip-guru-to-unveil-road-map-for-next-generation-hbmskorea-times-25-05-29\/","title":{"rendered":"AI memory chip guru to unveil road map for next-generation HBMs(Korea Times 25. 05. 29)"},"content":{"rendered":"

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Professor Kim Joung-ho\u2019s TERALAB at KAIST will host a technology presentation on June 11, unveiling a roadmap for next-generation HBM technologies, from HBM4 to HBM8. The event will also showcase key enabling technologies such as HBM architecture, performance, TSV, interposer, and cooling solutions, along with AI-based design automation research. The presentation will be broadcast live via ZOOM and later made available on YouTube, with plans to share the content with domestic and global semiconductor industries and to hold additional sessions overseas.<\/span><\/p>\n

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To respect media copyright, you can access the full article on the official Korea Times website.<\/span>

\n=> Go to Korea Times<\/a><\/span><\/p>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n

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