{"id":107228,"date":"2006-02-16T04:08:17","date_gmt":"2006-02-15T19:08:17","guid":{"rendered":"http:\/\/175.125.95.178\/press\/7228\/"},"modified":"2026-04-18T01:24:07","modified_gmt":"2026-04-17T16:24:07","slug":"7228","status":"publish","type":"press-post","link":"http:\/\/ee.presscat.kr\/en\/presses\/7228\/","title":{"rendered":"Kangmin lee won Outstanding Design Award  of Asian Solid-State Circuits Conference Design Contest"},"content":{"rendered":"<table border=\"0\" cellspacing=\"0\" cellpadding=\"0\" align=\"left\">\n<tr>\n<td><img decoding=\"async\" src=\"\/userfiles\/image\/article\/KangminLee-2.jpg\" alt=\"\" title=\"\"><\/td>\n<\/tr>\n<\/table>\n<p>A structured packet-switched Networks-on-Chip (NoC) is designed and implemented for high-performance heterogeneous SoC design platform. <br \/>The chip integrates multiprocessors, multiple memories, and other heterogeneous Intellectual Properties and interconnection with 51mW and 1.6GHz on-chip networks. <br \/>The NoC adopts a partial activated crossbar, low-energy coding, and low-swing signaling for the power consumption optimization. <br \/>A Network-in-Package integrating four NoCs is fabricated in a 676-BGA-type package for larger and scalable systems and demonstrates 2D-image-processing and 3D-graphics applications.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>663<\/p>\n","protected":false},"featured_media":0,"template":"","class_list":["post-107228","press-post","type-press-post","status-publish","hentry"],"acf":[],"_links":{"self":[{"href":"http:\/\/ee.presscat.kr\/en\/wp-json\/wp\/v2\/press-post\/107228","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/ee.presscat.kr\/en\/wp-json\/wp\/v2\/press-post"}],"about":[{"href":"http:\/\/ee.presscat.kr\/en\/wp-json\/wp\/v2\/types\/press-post"}],"wp:attachment":[{"href":"http:\/\/ee.presscat.kr\/en\/wp-json\/wp\/v2\/media?parent=107228"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}