Advanced Functional Materials<\/em> (2018.01)<\/p>\nThe use of von Neumann architecture, with its physically separate memory and processor, generates an extremely large energy-hungry data transfer between the memory and processor, inducing long latency and high power consumption. The memristor has been proposed as the fourth fundamental circuit element and can provide a creative solution to these problems. The memristor device has been widely investigated for a promising nonvolatile memory due to its simple structure, fast switching speed, low power consumption, and high packing density. The crossbar array is the optimal architecture enabling high packing density, defect tolerance, and logic operation; however, this architecture generates an inherent cell-to-cell interference problem. As this interference allows undesirable leakage currents known as \u201csneak currents\u201d to flow through unselected devices during memristor operations, it limits the maximum array size and prevents the memristive nonvolatile logic-in-memory circuit from enabling parallel computing.<\/p>\n
Herein, we develop a 1S\u20131M integrated circuit using a poly (1,3,5-trivinyl-1,3,5-trimethyl cyclotrisiloxane) (pV3D3)-based memristor and an a-IZTO-based selector on a flexible polyethersulfone (PES) substrate to propose a conceptual strategy for realizing an energy-efficient memristive nonvolatile logic-in-memory circuit, enabling parallel computing. The fabricated flexible a-IZTO-selector device exhibits outstanding stability against harsh electrical stress and mechanical strain. Using X-ray photoelectron spectroscopy (XPS) analysis and examining the I\u2013V characteristics, effective removal of the a-IZTO SEAL via oxygen plasma treatment is confirmed. Thanks to this reliable and flexible a-IZTO selector, the 1S\u20131M integrated devices exhibit a significantly reduced leakage current under a low-voltage region compared to a 1M device, along with reliable switching performance against electrical and mechanical stresses. The reading margin of the 1S\u20131M array is evaluated under various operational schemes (ground, V\/2, V\/3), indicating a feasible maximum array size of more than 1 Mbit. We also experimentally demonstrate that the fabricated 1S\u20131M array can perform single-instruction multiple-data (SIMD), the basis of parallel computing, without interruption by the sneak current. We strongly believe that the proposed parallel computing method using a memristive nonvolatile logic-in-memory circuit can provide a low-power circuit platform for battery-powered flexible electronic systems with various potential applications.<\/p>\n
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Figure 1.<\/strong> A<\/strong> Schematic illustration of integrated selector device role in memristor crossbar array during operation. B<\/strong> Cross-sectional TEM image of 1S\u20131M device. C<\/strong> Comparison of I\u2013V characteristics of 1S\u20131M and 1M devices. Inset: Nonlinear I\u2013V characteristics of 1S\u20131M device on linear scale compared with 1M device. D<\/strong> Calculated reading margin comparison for three reading bias schemes as function of array size. E<\/strong> Repetitive bending fatigue test for 1S\u20131M device. F<\/strong> Schematic of MAGIC-NOR gates within 1S\u20131M memristor array. G<\/strong> Experimental results for parallel operation of MAGIC-NOR gates.<\/p>\n![\"\"](\"http:\/\/ee.presscat.kr\/sites\/default\/files\/%ED%91%9C%EC%A7%80%EC%82%AC%EC%A7%842.jpg\" "\\"\\"")
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