{"id":134162,"date":"2022-10-04T14:20:25","date_gmt":"2022-10-04T05:20:25","guid":{"rendered":"http:\/\/192.249.19.202\/?post_type=ai-in-circuit&p=134162"},"modified":"2026-04-05T10:53:44","modified_gmt":"2026-04-05T01:53:44","slug":"kaist-ee-professor-hyun-sik-kims-team-prime-ministers-award-at-the-23rd-korea-semiconductor-design-challenge","status":"publish","type":"ai-in-circuit","link":"http:\/\/ee.presscat.kr\/en\/ai-in-circuit\/kaist-ee-professor-hyun-sik-kims-team-prime-ministers-award-at-the-23rd-korea-semiconductor-design-challenge\/","title":{"rendered":"KAIST EE Professor Hyun-Sik Kim\u2019s team, Prime Minister’s Award at the 23rd Korea Semiconductor Design Challenge"},"content":{"rendered":"
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[Prof. Hyun-Sik Kim, \u00a0PhD candidate\u00a0Gyuwan Lim, PhD candidate \u00a0Gyeong-Gu Kang, from left]<\/span><\/p>\n

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EE professor Hyun-Sik Kim\u2019s team of\u00a0Ph.D. students received\u00a0the Prime Minister’s Award at the 23rd Korea Semiconductor Design Challenge.<\/span><\/p>\n

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The 23rd<\/sup>\u00a0Korea Semiconductor Design Challenge is held to cultivate design skills and discover creative ideas of students within the field of semiconductor design, jointly organized by the Korean Ministry of Trade, Industry and Energy, and the Korea Semiconductor Industry Association (KSIA).<\/span><\/p>\n

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The winners, Gyuwan Lim and Gyeong-Gu Kang, have been selected for the achievement of high resolution and high uniformity with their mobile device Display Driver IC (DDI) design while maintaining an ultra-small chip area.<\/span><\/p>\n

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The DDI chip is a key component of a display system, that converts digital display data into analog signals (digital-to-analog conversion, DAC) and writes them to the display panel. The KAIST team solved the problem of uniformity and increasing chip surface that comes with higher resolution DDI chips.<\/span><\/p>\n

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The award-winning DDI chip design consists of a low-voltage MOSFET with a voltage amplifier instead of the conventional high-voltage MOSFET. This technology dramatically reduces the channel area, further reduced through a novel LSU technology that generates a 10-bit output voltage from an 8-bit input voltage.<\/span><\/p>\n

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The team was able to achieve high uniformity through designing a robust amplifier and chip operation against variations of the CMOS fabrication process. The novel DDI chip design is expected to significantly reduce cost while increasing the quality of mobile device displays through the reduced chip area, while achieving high resolution and high uniformity at the same time.<\/span><\/p>\n

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The results of this study were also presented at ISSCC 2022, a highly reputable international conference in the field of integrated circuits.<\/span><\/p>\n

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